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S5N8943B g.lite adsl analog front end ic preliminary information (revision 1.0) july 2000 samsung electronics confidential proprietary copyright ?1999-2000 samsung electronics, inc. all rights reserved
2 S5N8943B g.lite adsl analog front end ic confidential preliminary information (rev.1.0) contents page 1 overview ................................ ................................ ...................... 3 1.1 general description ................................ .............................. 3 1.2 features ................................ ................................ ................. 3 1.3 absolute maximum ratings ................................ .................. 4 1.4 electrical specifications ................................ ........................ 4 2 signal description ................................ ................................ ......... 6 2.1 functional block diagram ................................ .................... 6 2.2 i/o pins descriptions ................................ ............................ 7 2.3 pin configurations ................................ ................................ 9 3 block description ................................ ................................ ....... 10 3.1 adc/dac ................................ ................................ ............ 10 3.2 tx/rx lpf ................................ ................................ ........... 10 3.3 tx/rx agc ................................ ................................ ......... 10 4 digital signal interface ................................ ............................... 11 4.1 command signal interface ................................ .................. 11 4.2 data signal interface ................................ .......................... 18 5 application circuit ................................ ................................ ...... 19 5.1 atu-r ................................ ................................ ................. 19 5.2 atu-c ................................ ................................ ................. 20 6 package information ................................ ................................ .... 21
3 S5N8943B g.lite adsl analog front end ic confidential preliminary information (rev.1.0) 1. overview this chapter provides an overview of the S5N8943B01 adsl atu-c & atu-r analog front end chip. 1.1 general descriptions the S5N8943B01 is analog front end ic designed for dmt based universal adsl(asymmetric digital subscribe line) modems with 0.35u fully cmos technology. it has 25.875 ~ 138khz upstream channel and 142.312 ~ 552khz bandwidth downstream channel. the S5N8943B01 includes agc, lpf, adc, dac. the agc has 42db gain 0.4db step in rx mode and ? 24db gain 2db step in tx mode with 12bit/8bit control bits. anti alias lpf has 552khz passband frequency in rx path and 138khz in tx path. samsung ? s adsl afe chip provides 14bit adc at 2.208m, 4.416m or 8.832m sample rates and 14bit 4.416mhz, 8.832mhz dac. an 10bit dac support vcxo control for timing recovery. the vcxo is divided into a crystal driver at 35.328mhz. 1.2 features l integrated analog front end(afe) for adsl atu-c & atu-r l complies with g.lite l up to 552kbit/s down stream and 138kbit/s upstream channel l 14bit 2.208ms/s, 4.416ms/s or 8.832ms/s adc l 14bit 4.416mhz or 8.832mhz dac l 5 th -order low pass anti-alias filter tx/rx paths l rx 42db 0.4db step gain range with 12bit control signal l tx -24db 2db step gain range with 8bit control signal l 10bit 4khz vcxo dac l fully 0.35um cmos technology l 3.3v power supply operation l 0.4w power comsumption
4 S5N8943B g.lite adsl analog front end ic confidential preliminary information (rev.1.0) 1.3 absolute maximum ratings symbol parameter min typ max units v dd dc supply voltage -0.3 3.8 v dc input voltage -0.3 v dd +0.3 v v in 5v tolerant -0.3 5.5 v i in dc input current -10 10 ma t opr operation temperature -40 85 degree c t stg storage temperature -40 125 degree c 1.4 electrical specifications parameter min typ max units notes/conditions general power supply 3.0 3.3 3.6 v power consumption 450 mw normal operation rx path thd 70 snr 70 agc gain range 0 42 db 12bit control agc step size 0.4 db agc step error 0.2 db agc input range 2 vppd lpf cut off frequency 552 khz 5 th butterworth lpf output range 2 vppd lpf pass band ripple -0.5 0.5 db lpf stop band attenuation 60 db at 4.416mhz tx path thd 70 snr 70 agc gain range -24 0 db 8bit control agc step size 2 db agc step error 0.2 db agc output range 2 vppd lpf cut off frequency 138 khz 5 th chebyshev lpf pass band ripple -0.5 0.5 db lpf stop band attenuation 24 db at 276khz lpf input range 2 vppd adc
5 S5N8943B g.lite adsl analog front end ic confidential preliminary information (rev.1.0) resolution 14 bits effective number of bits 13 bits sampling rate 2.208 mhz selectable 4.416mhz, 8.832mhz full scale input range 2.0 vppd dac resolution 14 bits effective number of bits 12 bits sampling rate 4.416 mhz selectable 8.832mhz full scale output range 2.0 vppd vcxo dac resolution 10 bits sampling rate 4 khz maximum output range 2.5 v minimum output range 0.5 v
6 S5N8943B g.lite adsl analog front end ic confidential preliminary information (rev.1.0) 2. signal description 2.1 functional block diagram figure 2.1.1 S5N8943B01 functional block diagram 14bit adc rx lpf rx agc rx_inp rx_inn rx_data [13:0] control logic & register auto tunning bandgap & vi ref cbg auxclk 10bit dac cont_dax rx_inpg rx_inng rext sclk sdin sen resetn sdout 14bit dac tx lpf tx agc tx_outp tx_outn tx_data [13:0] mclk
7 S5N8943B g.lite adsl analog front end ic confidential preliminary information (rev.1.0) 2.2 i/o pins description signal name num type i/o description general pins resetn 48 cmos i system reset. active low cs1 49 cmos i chip select cs0 50 cmos i chip select tm1 51 cmos i digital interface selection ? 0 ? = 14bits , ? 1 ? =7bits*2 tm0 52 cmos i ? 0 ? = rt , ? 1 ? = co dac interface tx_data[13:0] 94~100, 1~7 cmos i dac 14bit data inputs if tm1=1, tx_data[13:7] is invalid mclk 8 cmos i master clock 4.416mhz(selectable 8.832m or 17.664m) auxclk 11 cmos i in 7bits data interface mode, auxclk=mclk/2 in 14bits data interface mode, pin is open or ground. tx_dacop 90 analog - dac current positive output for tx path tx_dacon 89 analog - dac current negative output for tx path comp_dac 88 analog - compensation capacitor 0.1uf connection for tx path iref_dac 87 analog - external resistor 1.24k connection adc interface rx_data[13:0] 12 ~ 25 cmos o adc 14bit data outputs ( if tm1=1, [13:7] is always low) rx_adcip 28 analog - adc positive input rx_adcin 29 analog - adc negative input bgr_adc 32 analog - adc band gap reference output reft_adc 33 analog - adc top reference output refb_adc 34 analog - adc bottom reference output dsp interface sclk 44 cmos i serial data clock sen 45 cmos i serial data enable sdout 46 cmos o serial data output sdin 47 cmos i serial data input tx pass interface tx_outp 78 analog - tx analog positive output tx_outn 77 analog - tx analog positive output tx_finp 85 analog - tx filter analog positive input tx_finn 86 analog - tx filter analog negative input rx pass interface rx_inp 58 analog - rx analog positive input rx_inn 57 analog - rx analog negative input rx_inpg 56 analog - rx analog external -14db gain positive input rx_inng 55 analog - rx analog external -14db gain negative input rx_foutp 31 analog - rx filter analog positive output rx_foutn 30 analog - rx filter analog negative output voltage reference
8 S5N8943B g.lite adsl analog front end ic confidential preliminary information (rev.1.0) tx_vcom 80 analog - tx pass common mode voltage rx_vcom 64 analog - rx pass common mode voltage cbg_ref 68 analog - bandgap reference compensation capacitor 100pf rext_ref 67 analog - reference current external resistor 6.8k vcxo interface cont_dax 40 analog - vcxo control voltage output (only rt) co pass (tm0 = ? 1 ? ) rx_aoutp 60 analog - rx agc analog positive output rx_aoutn 61 analog - rx agc analog negative output rx_finn 62 analog - rx filter analog negative input rx_finp 63 analog - rx filter analog positive input tx_ainp 81 analog - tx agc analog positive input tx_ainn 82 analog - tx agc analog positive input tx_foutn 83 analog - tx filter analog negative output tx_foutp 84 analog - tx filter analog negative output power supply avdd_dac 91 supply - tx analog dac vdd asub_dac 92 supply - tx analog dac sub avss_dac 93 supply - tx analog dac vss dvdd_dac 10 supply - tx digital dac vdd dvss_dac 9 supply - tx digital dac vss avdd_dax 38 supply - vcxo dac analog vdd avss_dax 39 supply - vcxo dac analog vss avdd_adc 35 supply - rx analog adc vdd asub_adc 36 supply - rx analog adc sub avss_adc 37 supply - rx analog adc vss dvdd_adc 27 supply - rx digital adc vdd dvss_adc 26 supply - rx digital adc vss avdd_tx 79 supply - tx path vdd avss_tx 76 supply - tx path vss asub_tx 75 supply - tx path sub avdd_fat 74 supply - filter auto tuning vdd avss_fat 71 supply - filter auto tuning vss avdd_rx 59 supply - rx filter vdd avss_rx 54 supply - rx filter vss asub_rx 53 supply - rx filter sub avdd_ref 69 supply - reference vdd avss_ref 66 supply - reference vss asub_ref 65 supply - reference sub dvdd_ctl 41 supply - control logic vdd dsub_ctl 42 supply - digital substrate vss dvss_ctl 43 supply - control logic vss
9 S5N8943B g.lite adsl analog front end ic confidential preliminary information (rev.1.0) 2.3 pin configurations ( top view) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 51 52 53 54 55 56 57 58 59 60 61 62 63 64 31 32 33 34 35 36 37 38 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 S5N8943B01 (100-qfp) avdd_adc asub_adc avss_adc rx_foutp avdd_dax avss_dax cont_dax dvdd_ctl dsub_ctl dvss_ctl sclk sen sdout sdin resetn cs1 cs0 tm1 tm0 asub_rx avss_rx avdd_rx rx_aoutn rx_aoutp rx_inng rx_inpg rx_inn rx_inp rx_vcom rx_finn rx_finp asub_ref avss_ref rext_ref cbg_ref avdd_ref asub_tx nc tx_outn tx_outp tx_vcom tx_ainp tx_dacon tx_ainn tx_dacop tx_finp tx_finn asub_dac avdd_dac avss_dac tx_data13 tx_data12 tx_data10 tx_data11 tx_data9 tx_data8 tx_data7 tx_data6 tx_data5 tx_data4 tx_data3 tx_data2 tx_data1 tx_data0 mclk dvss_dac dvdd_dac aux_clk rx_data0 rx_data1 rx_data2 rx_data3 rx_data4 rx_data5 rx_data6 rx_data7 rx_data8 rx_data9 rx_data10 rx_data11 rx_data12 rx_data13 dvss_adc dvdd_adc nc nc avdd_tx avss_tx tx_foutn tx_foutp iref_dac comp_dac bgr_adc reft_adc refb_adc rx_adcip rx_adcin rx_foutn avdd_fat avss_fat
10 S5N8943B g.lite adsl analog front end ic confidential preliminary information (rev.1.0) 3. block descriptions 3.1 adc / dac S5N8943B01 has a 14bit resolution adc 2.208m/4.416m/8.832m sample frequency. the input of adc is fully differential 2.0vppd max. the adc transforms the signal into a digital 14bit output. there are two type of dac ? s in S5N8943B01. one is for tx. it is 14bit 4.416mhz/8.832mhz frequency. samsung ? s dmt(s5n8944) transmit 14bit parallel data to the afe chip. the other dac is for vcxo control. it has 10bit resolution 4khz frequency. internal registers of S5N8943B01 transform 10bit vcxo control serial data from dsp into 10bit parallel data. and vcxo output analog signal cont_dax(pin #40). 3.2 tx/rx lpf 3.2.1 rx filters the combination of the external filter ( an lc ladder filter typically ) with the integrated low pass filter must provide: - dmt sidelobe and out of band ( anti-aliasing ) attenuation - anti alias filter ( 60db rejection @ image frequency ) - on chip tuning circuit included. 3.2.2 tx filters the tx filters act not only to suppress the dmt sidebands but also as smoothing filters on the d/a converter ? s output to suppress the image spectrum. for this reason they are realized in a time continuous approach and on chip tuning circuit included 3.3 tx/rx agc tx agc has 0~-24db gains with 2db step. it is controlled through 8bit serial digital signal from dsp. internal registers of samsung afe chips transform 8bit parallel control data. it outputs 2vppd fully differential signal to line driver. rx agc has low noise 0~42db gains with 0.4db step and it is controlled through 12bit + 1msb control signal. if 1msb is high, another rx input pass pin#55 rx_inng #56 rx_innp(external -14db gain pass) is seclected. it inputs 2vppd fully differential signal to rx lpf.
11 S5N8943B g.lite adsl analog front end ic confidential preliminary information (rev.1.0) 4. digital signal interface 4.1 command signal interface this description hold for atu-r (S5N8943B01). the chip consists of four kinds of register map: - power control - transmitter agc - receiver agc - vcxo control - clock selection serial interfaces use three pins: - clock - serial data input(25-bit: 2bit cs + 5bit address + 1bit r/w + 16 bit data + 1bit dummy) - serial data output(16 bit data) - enable serial data configuration serial data (sdat) cs address r / w data d u m m y register c s 1 c s 0 a 4 a 3 a 2 a 1 a 0 r / w d 1 5 d 1 4 d 1 3 d 1 2 d 1 1 d 1 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 x pwr_ctl c s 1 c s 0 x x 0 0 0 r / w x x x x x x x x p c 7 p c 6 p c 5 p c 4 p c 3 p c 2 p c 1 p c 0 x tx_agc c s 1 c s 0 x x 0 0 1 r / w x x x x x x x x t a 7 t a 6 t a 5 t a 4 t a 3 t a 2 t a 1 t a 0 x rx_agc c s 1 c s 0 x x 0 1 0 r / w x x x r a 1 2 r a 1 1 r a 1 0 r a 9 r a 8 r a 7 r a 6 r a 5 r a 4 r a 3 r a 2 r a 1 r a 0 x vcxo_ctl c s 1 c s 0 x x 0 1 1 r / w x x x x x x v c 9 v c 8 v c 7 v c 6 v c 5 v c 4 v c 3 v c 2 v c 1 v c 0 x clk_sel c s 1 c s 0 x x 1 0 0 r / w x x x x x x x x x x x x x x c k 1 c k 0 x x = don ? t care r/w =0 -> read r/w =1 -> write
12 S5N8943B g.lite adsl analog front end ic confidential preliminary information (rev.1.0) 4.1.1 register map 4.1.1.1 power control the power on/off control of afe blocks on this chip is set by the pwr_ctl register, (xx000), as described below: pwr_ctl register (a4a3a2a1a0=xx000) data d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 name pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 reset value 0 0 0 0 0 0 0 0 power control is as follow. pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 hex descripcion 0 0 0 0 0 0 0 0 0000 normal operation 0 0 0 0 0 0 0 1 0001 n/a 0 0 0 0 0 0 1 0 0002 n/a 0 0 0 0 0 1 0 0 0004 tx dac power down 0 0 0 0 1 0 0 0 0008 tx filter & agc power down 0 0 0 1 0 0 0 0 0010 rx adc power down 0 0 1 0 0 0 0 0 0020 rx filter power down 0 1 0 0 0 0 0 0 0040 rx agc power down 1 0 0 0 0 0 0 0 0080 vcxo dac power down adding power down (based on upper power down) 0 0 0 0 0 0 1 1 0003 n/a 0 0 0 0 1 1 0 0 000c tx path power down 0 1 1 1 0 0 0 0 0070 rx path power down 1 1 1 1 1 1 1 1 00ff whole chip power down
13 S5N8943B g.lite adsl analog front end ic confidential preliminary information (rev.1.0) 4.1.1.2 transmitter agc the main functions of the tx path are controlled by the tx_agc registers, as described below: tx_agc register (a4a3a2a1a0=xx001) data d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 name ta7 ta6 ta5 ta4 ta3 ta2 ta1 ta0 reset value 0 0 0 1 0 0 0 1 ta[7:0] tx path output attenuator gain setting. 0 to ? 24db attenuation in 2 db steps. (default is 0 db). ta[7] ta[6] ta[5] ta[4] ta[3] ta[2] ta[1] ta[0] hex gain(db) 0 0 0 1 0 0 0 1 0011 0 0 0 0 1 0 0 1 0 0012 -2 0 0 0 1 0 1 0 0 0014 -4 0 0 0 1 1 0 0 0 0018 -6 0 0 1 0 0 0 0 1 0021 -6 0 0 1 0 0 0 1 0 0022 -8 0 0 1 0 0 1 0 0 0024 -10 0 0 1 0 1 0 0 0 0028 -12 0 1 0 0 0 0 0 1 0041 -12 0 1 0 0 0 0 1 0 0042 -14 0 1 0 0 0 1 0 0 0044 -16 0 1 0 0 1 0 0 0 0048 -18 1 0 0 0 0 0 0 1 0081 -18 1 0 0 0 0 0 1 0 0082 -20 1 0 0 0 0 1 0 0 0084 -22 1 0 0 0 1 0 0 0 0088 -24
14 S5N8943B g.lite adsl analog front end ic confidential preliminary information (rev.1.0) 4.1.1.3 recieve agc the main functions of the rx path are controlled by the rx_agc register, as described below: rx_agc register (a4a3a2a1a0=xx010) data d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 name ra 12 ra 11 ra 10 ra9 ra8 ra7 ra6 ra4 ra4 ra3 ra2 ra1 ra0 reset value 0 0 0 0 0 1 0 0 1 0 0 0 0 ra[11:0]: receive path input gain setting 0 to 42db gain in 0.4 db steps. (default is 0 db). ra[12] is ? 1 ? ,the external attenuation gain(ex, ? 14db) path pin#55 rx_inng #56 rx_inpg will be enable. ra[12] should only be utilized the short line conditions. ra [12] ra [11] ra [10] ra [9] ra [8] ra [7] ra [6] ra [5] ra [4] ra [3] ra [2] ra [1] ra [0] hex gain(db) 1 0 0 0 0 1 0 0 1 0000 ~ 1111 1090~109f -14.0~-8.0 1 0 0 0 1 0 0 0 1 0000 ~ 1111 1110~111f -8.0~-2.0 1 0 0 1 0 0 0 0 1 0000 ~ 1111 1210~121f -2.0~4.0 0 0 0 0 0 1 0 0 1 0 0 0 0 0090 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0091 0.4 0 0 0 0 0 1 0 0 1 0 0 1 0 0092 0.8 0 0 0 0 0 1 0 0 1 0 0 1 1 0093 1.2 0 0 0 0 0 1 0 0 1 0 1 0 0 0094 1.6 0 0 0 0 0 1 0 0 1 0 1 0 1 0095 2.0 0 0 0 0 0 1 0 0 1 0 1 1 0 0096 2.4 0 0 0 0 0 1 0 0 1 0 1 1 1 0097 2.8 0 0 0 0 0 1 0 0 1 1 0 0 0 0098 3.2 0 0 0 0 0 1 0 0 1 1 0 0 1 0099 3.6 0 0 0 0 0 1 0 0 1 1 0 1 0 009a 4.0 0 0 0 0 0 1 0 0 1 1 0 1 1 009b 4.4 0 0 0 0 0 1 0 0 1 1 1 0 0 009c 4.8 0 0 0 0 0 1 0 0 1 1 1 0 1 009d 5.2 0 0 0 0 0 1 0 0 1 1 1 1 0 009e 5.6 0 0 0 0 0 1 0 0 1 1 1 1 1 009f 6.0 0 0 0 0 1 0 0 0 1 0000 ~ 1111 0110~011f 6.0~12.0 0 0 0 1 0 0 0 0 1 0000 ~ 1111 0210~021f 12.0~18.0 0 0 1 0 0 0 0 0 1 0000 ~ 1111 0410~041f 18.0~24.0 0 1 0 0 0 0 0 0 1 0000 ~ 1111 0810~081f 24.0~30.0 0 1 0 0 0 0 0 1 0 0000 ~ 1111 0820~082f 30.0~36.0 0 1 0 0 0 0 1 0 0 0000 ~ 1111 0840~084f 36.0~42.0
15 S5N8943B g.lite adsl analog front end ic confidential preliminary information (rev.1.0) 4.1.1.4 vcxo control the vcxo dac is 10-bit voltage-mode dac designed to be monotonic and intended to be operated at a 4 khz update rate. in order to update the dac, the user must write to the vcxo register through the serial port. the individual bit definitions are given below. vcxo_ctl register (a4a3a2a1a0=xx011) data d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 name vc9 vc8 vc7 vc6 vc4 vc4 vc3 vc2 vc1 vc0 reset value 1 0 0 0 0 0 0 0 0 0 vc[9:0]: vcxo dac 10-bit word. the dac nominal output voltages for extreme and mid-scale codes are as follows. vc[9:0] = 0000000000 = 0.5 v vc[9:0] = 1000000000 = 1.5 v (mid-range) vc[9:0] = 1111111111 = 2.5 v a general expression for the dac output voltage is 0.5 v + (code / 1024) x (2.0 v) where code is the decimal integer value of the 10-bit word formed by vcxo[9:0].
16 S5N8943B g.lite adsl analog front end ic confidential preliminary information (rev.1.0) 4.1.1.5 clock selection main functions of clock selection are frequency selection of each mclk/auxclk/adc. the individual bit definitions are given below. clk_sel register (a4a3a2a1a0=xx100) data d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 name ck1 ck0 reset value 0 0 tm1, ck[1:0] : clock selection has eight possible clocking configuration as follow. tm1 2 phase ck1 ck0 hex mclk auxclk dac adc 0 off 0 0 0000 4.416 mhz 0 4.416 mhz 2.208 mhz 0 off 0 1 0001 4.416 mhz 0 4.416 mhz 4.416 mhz 0 off 1 0 0002 8.832mhz 0 8.832mhz 4.416 mhz 0 off 1 1 0003 8.832mhz 0 8.832mhz 8.832mhz 1 on 0 0 0000 8.832mhz 4.416 mhz 4.416 mhz 4.416 mhz 1 on 0 1 0001 8.832mhz 4.416 mhz 4.416 mhz 2.204 mhz 1 on 1 0 0002 17.664mhz 8.832mhz 8.832mhz 8.832 mhz 1 on 1 1 0003 17.664mhz 8.832mhz 8.832mhz 4.416 mhz
17 S5N8943B g.lite adsl analog front end ic confidential preliminary information (rev.1.0) 4.1.2 serial data interface 4.1.2.1 physical interface serial interfaces use three pins: - clock - serial data (25-bit: 2bit cs + 5bit address + 1bit r/w + 16 bit data + 1bit dummy) - enable s5n8944 (dmt) S5N8943B01 (afe) afe_sclk afe_sen afe_sdin 4.1.2.2 waveform parameter symbol min typ max unit sclk clock period t cyc 905 ns sclk high time t pwh 452 ns sclk low time t pwl 452 ns sen low to sclk high t su1 30 ns sclk high to sen high t h1 15 ns sen inactive pulse time t pw 905 ns sdin setup time t su2 15 ns sdin hold time t h2 15 ns sclk low to sdout delay t d3 30 ns sen inactive to sdout hiz t d4 30 ns cs1 sclk sdin sen cs0 a4 a3 a2 a1 a0 r/w d15 d14 d1 d0 dummy t su1 t pwl t cyc t pwh t h1 t pw t h2 t su2 sdout d15 d14 d1 d0 t d4 t d3
18 S5N8943B g.lite adsl analog front end ic confidential preliminary information (rev.1.0) 4.2 data interface 4.2.1 physical interface l adc and dac data transmission between S5N8943B01 and s5n8944 l parallel interface(s5n8944) : 29 pin (14 adc bit data, 14 dac bit data, mclk) l parallel interface : 16 pin ( 7 adc bit data, 7 dac bit data, mclk,auxclk) s5n8944 (dmt) S5N8943B01 (afe) mclk tx_data[13:0] rx_data[13:0] auxclk 4.2.2 waveform figure 4.2.1 waveform of 14bit parallel interface (tm1=0) figure 4.2.2 waveform of 7bit parallel interface (tm1=1) parameter symbol min typ max unit note mclk clock period t cyc 226 ns mclk=4.416mhz mclk high time t pwh 113 ns mclk=4.416mhz mclk low time t pwl 113 ns mclk=4.416mhz data delay after mclk t d 10 ns rx_data setup to mclk t su 30 ns mclk=4.416mhz rx_data hold to mclk t h 84 ns mclk=4.416mhz auxclk setup to mclk t su2 10 ns auxclk hold to mclk t h2 10 ns tx_data[13:0] tx_data[13:0] tx_data[13:0] mclk tx_data rx_data tx_data[13:0] rx_data[13:0] rx_data[13:0] t pwh t pwl t d t d t su t h t cyc auxclk tx_data[6:0] tx_data [6:0] mclk tx_data tx_data13:7] t d tx_data[13:7] t su2 t h2 rx_data[6:0] rx_data[6:0] rx_data rx_data[13:7] rx_data[13:7] n-1 n-1 n n n-1 n-1 n n
19 S5N8943B g.lite adsl analog front end ic confidential preliminary information (rev.1.0) 5. application circuit 5.1 atu-r 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 85 84 83 82 81 91 90 89 88 87 86 100 99 98 97 96 95 94 93 92 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 da<13:0> ad<13:0> mclk sclk sen sdout sdin s5n8944 interface resetn cs1 cs0 p1 1.24k 0.1u 0.0375k 0.0375k vcxo rx_inp 39n 39n 39n 39n rx_inn system interface line interface g1 g2 p2 g3 p3 p4 g4 p5 g5 p6 g7 g8 p8 10u 0.1u 10u 0.1u p5 g5 10u 0.1u p6 g6 10u 0.1u p7 g7 10u 0.1u p1 g1 10u 0.1u p2 g2 10u 0.1u p3 g3 10u 0.1u p4 g4 10u 0.1u p8 g8 10u 0.1u p9 g9 p6 g6 100p 6.8k g6 S5N8943B01 (100qfp) tx_data6 tx_data5 tx_data4 tx_data3 tx_data2 tx_data1 tx_data0 mclk dvss_dac dvdd_dac auxclk rx_data0 rx_data1 rx_data2 rx_data3 rx_data4 rx_data5 rx_data6 rx_data7 rx_data8 rx_data9 rx_data10 rx_data11 rx_data12 rx_data13 dvss_adc dvdd_adc dvdd_ctl dsub_ctl dvss_ctl sclk sen sdout sdin resetn avdd_adc asub_adc avss_adc rx_foutp avdd_dax avss_dax cont_dax cs1 cs0 tm1 tm0 asub_rx avss_rx avdd_rx rx_aoutp rx_aoutn rx_inng rx_inpg rx_inn rx_inp rx_vcom rx_finn rx_finp asub_ref avss_ref rext_ref cbg_ref avdd_ref asub_tx avss_tx nc nc avdd_tx tx_vcom tx_outn tx_outp tx_finp tx_finn tx_dacon tx_dacop iref_dac comp_dac avdd_dac asub_dac avss_dac tx_data13 tx_data12 tx_data11 tx_data10 tx_data9 tx_data8 tx_data7 auxclk p7 tx_outp tx_outn 5.1k 5.1k g10 p10 39n 39n 1u 0.1u 0.1u 1k 1k 12 bgr_adc reft_adc refb_adc rx_adcip rx_adcin rx_foutn 0.1u 0.1u 10u 0.1u 10u 0.1u tx_foutp tx_ainn tx_foutn tx_ainp 1k 1k 1k 4.3k 1k 4.3k 1u avdd_fat avss_fat nc p9 p9 10u 0.1u p10 g10
20 S5N8943B g.lite adsl analog front end ic confidential preliminary information (rev.1.0) 5.2 atu-c 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 85 84 83 82 81 91 90 89 88 87 86 100 99 98 97 96 95 94 93 92 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 da<13:0> ad<13:0> mclk sclk sen sdout sdin s5n8944 interface resetn cs1 cs0 p1 1.24k 0.1u 0.0375k 0.0375k vcxo rx_inp 39n 39n 39n 39n rx_inn system interface line interface g1 g2 p2 g3 p3 p4 g4 p5 g5 p6 g7 g8 p8 10u 0.1u 10u 0.1u p5 g5 10u 0.1u p6 g6 10u 0.1u p7 g7 10u 0.1u p1 g1 10u 0.1u p2 g2 10u 0.1u p3 g3 10u 0.1u p4 g4 10u 0.1u p8 g8 10u 0.1u p9 g9 p6 g6 100p 6.8k g6 S5N8943B01 (100qfp) tx_data6 tx_data5 tx_data4 tx_data3 tx_data2 tx_data1 tx_data0 mclk dvss_dac dvdd_dac auxclk rx_data0 rx_data1 rx_data2 rx_data3 rx_data4 rx_data5 rx_data6 rx_data7 rx_data8 rx_data9 rx_data10 rx_data11 rx_data12 rx_data13 dvss_adc dvdd_adc dvdd_ctl dsub_ctl dvss_ctl sclk sen sdout sdin resetn avdd_adc asub_adc avss_adc rx_foutp avdd_dax avss_dax cont_dax cs1 cs0 tm1 tm0 asub_rx avss_rx avdd_rx rx_aoutp rx_aoutn rx_inng rx_inpg rx_inn rx_inp rx_vcom rx_finn rx_finp asub_ref avss_ref nc rext_ref cbg_ref avdd_ref asub_tx avss_tx nc nc avdd_tx tx_vcom tx_outn tx_outp tx_finp tx_finn tx_dacon tx_dacop iref_dac comp_dac avdd_dac asub_dac avss_dac tx_data13 tx_data12 tx_data11 tx_data10 tx_data9 tx_data8 tx_data7 auxclk p7 tx_outp tx_outn 5.1k 5.1k g10 p10 39n 39n 1u 0.1u 0.1u 1k 1k 12 bgr_adc reft_adc refb_adc rx_adcip rx_adcin rx_foutn 0.1u 0.1u 10u 0.1u 10u 0.1u tx_foutp tx_ainn tx_foutn tx_ainp 1k 1k 1k 4.3k 1k 4.3k 1u j3 j2 j1 j2 j3 j7 j6 j5 j6 j4 j5 j7 j8 j1 j4 j8 10u 0.1u p10 g10 avdd_fat avss_fat p9 g9
21 S5N8943B g.lite adsl analog front end ic confidential preliminary information (rev.1.0) 6. package information (100qfp-1420c)
22 S5N8943B g.lite adsl analog front end ic confidential preliminary information (rev.1.0) revision history revision no. date description 1.0 2000-07-20 S5N8943B (rev.1) released. important notice the information furnished by samsung electronics in this document is belived to be accurate and reliable. however, no resposibility is assumed by samsung electronics for its use, nor for any infringements of patents or other rights of third parties resulting from its use. no license is granted under any patents or patent rights of samsung electronics. samsung electronics reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current and complete. for more information tel: (82)-(31)-209-8301, fax: (82)-(31)-209-8309 e-mail: kimil@sec.samsung.com http://www.intl.samsungsemi.com copyright ?2000 samsung electronics, inc. all rights reserved

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